Time division multiplexing shared memory

Abstract

Systems and methods related to time division multiplexing shared memories are disclosed herein. A shared memory system may use time division access techniques, lane access techniques, or both to reduce the complexity of cross bar circuits while maintaining high throughput. The memory system may comprise a set of port groups, a set of selection circuits coupled to the set of port groups in a one-to-one correspondence, a set of memory banks, and a time division multiplexing control system. The time division multiplexing control system may be coupled to a set of control inputs of the set of selection circuits, and may be configured to couple, in a cycle of one-to-one correspondences, the set of port groups to the set of memory banks. The memory system may divide memory banks and client ports into separate lanes based on address bits, where each lane operates independently with dedicated routing circuits.

Dependencies are inferred from the claim text.