Multi-processing unit status aggregation and transmission

A system, comprising:

• a plurality of processing units (PUs), each PU of the plurality of PUs including an output data path to transmit respective processor information signals;
• a baseboard management controller (BMC) configured to receive the respective processor information signals;
• and
• an aggregator communicatively coupled between the plurality of PUs and the BMC, wherein each output data path for the PUs of the plurality of PUs is coupled to the aggregator and the aggregator is configured to:
• receive the respective processor information signals from the plurality of PUs;
• identify, based at least in part on a start sequence and an address, a first processor information signal;
• transmit a first data stream associated with the first processor information signal to the BMC;
• and
• maintain the remaining PUs in a clock stretch operating condition while transmitting the first data stream.

A system, comprising:

• a plurality of processing units (PUs), each PU of the plurality of PUs including an output data path to transmit respective processor information signals;
• a controller configured to receive the respective processor information signals;
• and
• an aggregator communicatively between the plurality of PUs and the controller;
• wherein each output data path for the respective PUs of the plurality of PUs is coupled to the aggregator, a processor information signal communication path is formed between the controller and the aggregator, and the plurality of PUs are not directly coupled to the controller with individual processor information signal communication paths.