Method and system for optimizing power consumption in system on chip during warm boot

A system for optimizing power consumption in a system on chip (SoC) during warm boot, the system comprising:

• a memory storing a program of instructions;
• a processor coupled with the memory;
• a power management unit coupled to the memory and the processor. wherein the processor is configured to execute the program of instructions to
• identify one or more groups of interdependent hardware peripherals on the SoC, wherein an interdependency among at least two interdependent hardware peripherals within each group of the one or more groups of interdependent hardware peripherals corresponds to an initialization sequence of the at least two interdependent hardware peripherals;
• wherein the power management unit is configured to determine power consumed by the one or more groups of interdependent hardware peripherals during the warm boot of the SoC;
• wherein the processor is further configured to
• create a subset from among the one or more groups of interdependent hardware peripherals, wherein the power consumed during the warm boot by the at least two interdependent hardware peripherals in the subset is below a power consumption threshold;
• and
• generate, based on the subset from among the one or more groups of interdependent hardware peripherals, a file with a load region and an execution region for the subset.

A method of an initialization sequence of a system on chip (SoC), the method comprising:

• executing, by a power management controller (PMC), a boot read-only memory (ROM) power on reset;
• loading, by the PMC, platform firmware into a peripheral protection unit (PPU) random-access memory (RAM);
• and
• performing, by the PMC, a network-on-chip (NoC) and a double data rate (DDR) configuration and a reset of a real-time processor unit (RPU).