Mapping memory addresses from single instruction, multiple thread (simt) processor to memory banks of banked memory in different ways during runtime
OwnerMartin Langhammerinventor
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OwnerMartin Langhammerinventor
Estimating the term…
A processor of an aspect includes a banked memory. The banked memory has a plurality of memory banks. The processor also includes a single instruction, multiple thread (SIMT) processor. The SIMT processor includes a plurality of processor elements. The processor elements are to perform memory access operations with memory addresses. The processor also includes banked memory access circuitry coupled with the banked memory, and coupled with the SIMT processor. The banked memory access circuitry is to access data in the banked memory with each of the memory addresses. The banked memory access circuitry is reconfigurable during runtime to map the memory addresses to the memory banks in a plurality of different ways. Other processors, methods, systems, and non-transitory machine-readable storage mediums are also disclosed.
A processor comprising:
A method comprising:
A machine-readable storage medium storing instructions that if executed cause a machine to perform operations, comprising to:
Dependencies are inferred from the claim text.