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US 2026/0064427 A1Published application
Sequentially clearing subsets of prediction state of processors while continuing to process instructions
AssigneeIntel Corporation
InventorsMathew Lowes, Martin Licht, Priyanka Gupta, Jared Warner Stark, IV, Jonathan Combs
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Abstract
A method of an aspect includes processing instructions with a processor, making predictions associated with some of the instructions based on prediction state, clearing a plurality of subsets of the prediction state sequentially, and continuing the processing of the instructions while the plurality of the subsets of the prediction state are being cleared. Other methods, processors, and systems are also disclosed.
Claims20
A method comprising:
- processing instructions with a processor;
- making predictions associated with some of the instructions based on prediction state;
- clearing a plurality of subsets of the prediction state sequentially;
- and
- continuing the processing of the instructions while the plurality of the subsets of the prediction state are being cleared.
2 more elements
A processor comprising:
- a front-end unit to obtain and decode instructions, the front-end unit including:
- a prediction unit having storage to store prediction state, the prediction unit to make predictions associated with some of the instructions based on the prediction state;
- and
- circuitry to sequentially clear a plurality of subsets of the prediction state;
- and
- a back-end unit coupled with the front-end unit, the back-end unit to execute and commit the instructions,
- wherein the processor is to continue to process the instructions, while the plurality of the subsets of the prediction state are being cleared.
4 more elements
A system comprising:
- a processor, the processor comprising:
- a prediction unit to make predictions using prediction state;
- a fetch unit to fetch instructions based on the predictions;
- a decode unit to decode the instructions;
- a plurality of execution units to perform operations corresponding to the instructions;
- and
- circuitry to sequentially clear a plurality of subsets of the prediction state,
- wherein, while the plurality of the subsets of the prediction state are being sequentially cleared, the fetch unit is to fetch additional instructions, the decode unit is to decode the additional instructions, and the plurality of execution units are to perform operations corresponding to the additional instructions;
- and
- a dynamic random access memory (DRAM) coupled with the processor.
7 more elements
Dependencies are inferred from the claim text.