Mitigating slow read disturb in a memory sub-system
AssigneeMicron Technology, Inc.
InventorsVamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Giuseppina Puzzilli, Saeed Sharifi Tehrani
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AssigneeMicron Technology, Inc.
InventorsVamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Giuseppina Puzzilli, Saeed Sharifi Tehrani
Estimating the term…
Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to receiving a read request to perform a read operation on a block of the memory device, incrementing a counter associated with the block to track a number of read operations performed on the block; setting a timer associated with the block to an initial value; determining that respective values of the counter and the timer are indicative of a minimum number of read operations performed on the block; and issuing a voltage discharge command to the block, wherein issuing the voltage discharge command results in the block reaching a ground voltage.
A system comprising:
A method comprising:
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
Dependencies are inferred from the claim text.