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US 2026/0064282 A1Published application
Storage device for reducing delay of parity operation, controller and method for operating controller
AssigneeSK hynix Inc.
InventorsHyo Jin CHOI, Kwan Su LEE
Life of this patent
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Abstract
A first processor manages state information of a buffer area of a buffer memory used as a parity area in a parity operation mode and outputs a control signal according to the state information, and a second processor which performs a parity operation using the buffer area performs the parity operation according to the control signal of the first processor.
Claims20
A storage device, comprising:
- a controller configured to manage data storing operations,
- wherein the controller comprising:
- a first processor configured to manage state information for a plurality of buffer areas and to generate a control signal based on the state information;
- and
- a second processor configured to store data into the plurality of buffer areas according to the control signal provided from the first processor,
- wherein the first processor is configured to manage the state information of the buffer areas while the second processor is performing the data storing operations.
3 more elements
A controller configured to manage data storing operations, comprising:
- a first processor configured to manage state information for a plurality of buffer areas and to generate a control signal based on the state information;
- and
- a second processor configured to state data in the plurality of buffer areas according to control signal provided from the first processor,
- wherein the first processor is configured to manage the state information of the buffer areas which the second processor is performing the data storing operations.
1 more element
Dependencies are inferred from the claim text.