Fully integrated process monitor and threshold voltage extractor circuit

A process monitor for a transistor device comprising:

• a current source circuitry configured to provide an input current (IIN) to a drain of at least one Device Under Test (DUT), which comprises an NMOS (n-type metal oxide semiconductor) or a PMOS (n-type metal oxide semiconductor);
• a drain-source voltage regulation circuitry configured to regulate a drain-source voltage (referred to as VDS for NMOS, VSD for PMOS) of said at least one DUT;
• a gate-source voltage regulation circuitry configured to regulate a gate-source voltage (VGS) of said at least one DUT versus said input current so that said drain-source voltage remains constant and said at least one DUT is in a linear region or in a saturation region or between the linear and saturation regions;
• and
• a measurement circuitry configured to measure said gate-source voltage to derive therefrom an operational parameter of said transistor device.