Semiconductor structure

A structure, comprising:

• a transistor array, comprising:
• a first transistor, which comprises:
• a first channel layer, wherein the first channel layer is a crystalline layer;
• a magnesium oxide layer disposed below the first channel layer;
• a second transistor, which comprises:
• a second channel layer, wherein the second channel layer is an amorphous channel layer;
• a dielectric layer covering a bottom surface of the second channel layer, and laterally surrounding the first channel layer and the magnesium oxide layer.

A structure, comprising:

• a plurality of conductive layers;
• a plurality of transistors electrically connected to the plurality of conductive layers, wherein the plurality of transistors comprises:
• a first channel layer;
• a first magnesium oxide layer located below the first channel layer and extending beyond sidewalls of the first channel layer;
• a second magnesium oxide layer located below the first magnesium oxide layer;
• a high-k dielectric layer disposed in between the first magnesium oxide layer and the second magnesium oxide layer, wherein sidewalls of the high-k dielectric layer is aligned with sidewalls of the first magnesium oxide layer, and aligned with sidewalls of the second magnesium oxide layer;
• and
• a first gate electrode disposed below the second magnesium oxide layer.