Gate driver architecture for hybrid sic mosfet and si igbt power semiconductor device

A gate driver integrated chip comprising:

• a high voltage side and a low voltage side, wherein the high voltage side is insulated from the low voltage side;
• two or more output stages on the high voltage side configured to transmit a first voltage to a silicon carbide metal-oxide-semiconductor field-effect transistor, SiC MOSFET, and transmit a second voltage to a silicon insulated-gate bipolar transistor, Si IGBT;
• a first controller on the low voltage side;
• a second controller on the high voltage side in communication with the two or more output stages;
• and
• an analogue-to-digital, ADC, circuit on the high voltage side;
• wherein the first controller is in communication with both the ADC circuit and the second controller;
• wherein the ADC circuit is in further communication with the second controller;
• wherein the ADC circuit is configured to receive an inverter output current, a SiC MOSFET temperature, and a Si IGBT temperature;
• wherein the first controller is configured to:
• receive the inverter output current, the SiC MOSFET temperature, and the Si IGBT temperature via the ADC circuit;
• determine a temperature difference based on the inverter output current, wherein the temperature difference is a difference between the SiC MOSFET temperature and the Si IGBT temperature;
• and
• adjust a first current and a second current based on the temperature difference and determine an operation mode;
• wherein the second controller is configured to:
• receive a mode information of the operation mode from the first controller;
• receive a temperature difference from the first controller;
• determine a first time difference and a second time difference, wherein the first time difference is a time difference between a time when the first output stage switches on and a time when the second output stage switches on and the second time difference is a time difference between a time when the first output stage switches off and a time when the second output stage switches off based on the temperature difference and the mode information;
• and
• control at least one gate of the two or more output stages based on the first time difference and the second time difference.