US 2026/0040945 A1Published application

Single die reinforced galvanic isolation device

OwnerJeffrey Alan West, Thomas Dyer Bonifield +2inventors

InventorsJeffrey Alan West, Thomas Dyer Bonifield, Toshiyuki Tamura, Yoshihiro Takei

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Abstract

A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.

Claims12

Dependent claims

A method of forming a microelectronic device, comprising:

forming an inorganic dielectric on a substrate;
forming an isolation device including;
forming a plateau, forming the plateau including;
forming a lower dielectric stack on the inorganic dielectric containing at least one low stress silicon dioxide layer, and at least one high stress silicon dioxide layer;
forming a lower isolation element in the lower dielectric stack;
forming a middle dielectric stack on the lower dielectric stack, the middle dielectric stack including a lower etch stop layer, an upper etch stop layer, and at least one layer of low stress silicon dioxide and at least one layer of high stress silicon dioxide between the lower etch stop layer and the upper etch stop layer;
forming an upper dielectric stack on the middle dielectric stack including at least one layer of low stress silicon dioxide, at least one layer of high stress silicon dioxide, at least one layer of silicon oxynitride and at least one layer of silicon nitride;
and
forming an upper isolation element on the upper dielectric stack;
forming an upper bond pad in electrical contact with upper isolation element;
and
forming a lower bond pad in electrical connection with the lower isolation element.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/357,743Filed 14 Oct 2025
Priority: 30 Sep 2022
Published: 5 Feb 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10W 42/00
Arrangements for protection of devices
H10W 44/501
Electrical arrangements for controlling or matching impedance: inductive arrangements
H10D 1/20
Resistors, capacitors or inductors: inductors
H10W 10/011
Manufacture or treatment: of isolation regions comprising dielectric materials

Family

Application17/958,040Division · filed 30 Sep 2022
Application19/357,743Division
US 12,463,153 B2Related patent
US 2024/0113042 A1Published application
US 2026/0040945 A1This patent

From the US filing history. Foreign family members aren’t listed.

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