Rivet isolation and method
AssigneeMicron Technology, Inc.
InventorsJiewei Chen, Jordan D. Greenlee, Sundar Rajarajan
Life of this patent
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Abstract
Apparatus and methods are disclosed, including interconnection pathways, vias, memory cells, semiconductor devices and systems. Example semiconductor devices and methods include a conducting via passing between a top level of a stack and a bottom level of the stack. One or more isolation layers surround sides and a bottom of the conducting via. A lateral connection is shown between a location along the conducting via and a selected conductor layer from the stack, the lateral connection passing through the isolation layer.
Claims21
A memory device, comprising;
- a stack of alternating dielectric layers and conductor layers;
- a number of memory cells formed within the stack of alternating dielectric layers and conductor layers;
- a conducting via passing between a top level of the stack and a bottom level of the stack;
- an isolation layer surrounding sides and a bottom of the conducting via;
- and
- a lateral connection between a location along the conducting via and a selected conductor layer from the stack, the lateral connection passing through the isolation layer.
A memory device, comprising;
- a stack of alternating dielectric layers and conductor layers;
- a number of memory cells formed within the stack of alternating dielectric layers and conductor layers;
- a conducting via passing between a top level of the stack and a bottom level of the stack;
- a first isolation layer surrounding sides of the conducting via;
- a second isolation layer between a bottom of the conducting via and a substrate;
- and
- a lateral connection between a location along the conducting via and a selected conductor layer from the stack, the lateral connection passing through the first isolation layer.
A method of forming a memory device, comprising:
- forming a vertical cavity through a stack of alternating dielectric layers and conductor layers;
- forming a lateral cavity connected to the vertical cavity, the lateral cavity located at a selected conductor layer in the stack;
- filling the lateral cavity with a second conductor and forming a second conductor liner on sidewalls of the vertical cavity;
- removing the second conductor liner from sidewalls of the vertical cavity, leaving an exposed second conductor at the selected conductor layer in the stack;
- forming a self-aligning isolation layer on sidewalls and a bottom of the vertical cavity, wherein the self-aligning isolation layer does not adhere to the exposed second conductor;
- and
- forming a conducting via over the self-aligning isolation layer and coupled to the exposed second conductor.
Dependencies are inferred from the claim text.