Magnetic memory device including a magnetic tunnel junction and a method of manufacturing the magnetic memory device

A magnetic memory device comprising:

• a substrate having first and second surfaces facing each other;
• a first active region disposed on the first surface of the substrate, wherein the first active region includes a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern;
• a first interlayer insulating layer covering the lower source/drain pattern;
• a first active contact extending from an upper surface of the first interlayer insulating layer into an interior of the lower source/drain pattern;
• an upper insulating layer disposed on the first interlayer insulating layer;
• a first magnetic tunnel junction pattern disposed in the upper insulating layer, wherein the first magnetic tunnel junction pattern is connected to the first active contact through an interlayer wiring;
• a backside wiring layer disposed on the lower surface of the substrate;
• a second magnetic tunnel junction pattern disposed in the backside wiring layer;
• and
• a second active contact extending from the lower surface of the substrate into the interior of the lower source/drain pattern and being connected to the second magnetic tunnel junction pattern,
• wherein each of the first and second magnetic tunnel junction patterns includes a pinned magnetic pattern, a free magnetic pattern, and a tunnel barrier pattern therebetween, and
• wherein the tunnel barrier pattern of the first magnetic tunnel junction pattern is insulated-broken and has an irreversible resistance state.

A magnetic memory device comprising:

• a magnetic memory device having a substrate having upper and lower surfaces facing each other, wherein the substrate includes an active pattern;
• a first active region disposed on the active pattern, wherein the first active region includes a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern;
• a second active region stacked on the first active region, wherein the second active region includes an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern;
• a gate electrode disposed on the lower channel pattern and the upper channel pattern, wherein the gate electrode extends in a first direction;
• an interlayer insulating layer covering the lower and upper source/drain patterns;
• a first active contact extending from an upper surface of the interlayer insulating layer into an interior of the upper source/drain pattern;
• an upper insulating layer disposed on the interlayer insulating layer;
• a wiring insulating layer disposed on the upper insulating layer;
• a first wiring disposed on the wiring insulating layer;
• a first magnetic tunnel junction pattern in the upper insulating layer, wherein the first magnetic tunnel junction pattern is connected to the first active contact through interlayer wiring and upper vias, and connected to the first wiring through upper wiring and upper connection line in the wiring insulating layer;
• a backside wiring layer disposed on the lower surface of the substrate;
• a second magnetic tunnel junction pattern and a lower wiring disposed in the backside wiring layer, wherein the second magnetic tunnel junction pattern is disposed between the substrate and the lower wiring;
• a second active contact extends from the lower surface of the substrate into the lower source/drain pattern and connected to the second magnetic tunnel junction pattern;
• a lower via connecting the lower wiring and the second magnetic tunnel junction pattern to each other;
• and
• a through-contact plug penetrating the upper insulating layer, the interlayer insulating layer, and the substrate, and penetrating a portion of the backside wiring layer to connect the upper wiring and the lower wiring to each other.