Semiconductor device

A semiconductor device comprising,

• a substrate;
• a first active pattern extending in a first horizontal direction on the substrate;
• a second active pattern extending in the first horizontal direction on the substrate, the second active pattern being spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction,
• a first plurality of nanosheets, each nanosheet of the first plurality of nanosheets being stacked and spaced apart from each other in a vertical direction on the first active pattern, each nanosheet of the first plurality of nanosheets having two sidewalls;
• a second plurality of nanosheets, each nanosheet of the second plurality of nanosheets being stacked and spaced apart from each other in the vertical direction on the second active pattern, a second width of each nanosheet of the second plurality of nanosheets in the second horizontal direction being greater than a first width of each nanosheet of the first plurality of nanosheets in the second horizontal direction, each nanosheet of the second plurality of nanosheets having two sidewalls;
• a gate electrode extending in the second horizontal direction on the first and second active patterns, the gate electrode surrounding each nanosheet of the first plurality of nanosheets and each nanosheet of the second plurality of nanosheets, the gate electrode having two sidewalls;
• a first source/drain region being in contact with both of the two sidewalls in the first horizontal direction of each nanosheet of the first plurality of nanosheets on the first active pattern;
• a second source/drain region being in contact with both of the two sidewalls in the first horizontal direction of each nanosheet of the second plurality of nanosheets on the second active pattern;
• a first inner spacer disposed between the gate electrode and the first source/drain region;
• and
• a second inner spacer disposed between the gate electrode and the second source/drain region,
• wherein a first portion of the first inner spacer overlaps with the second inner spacer in the second horizontal direction, and a second portion of the first inner spacer does not overlap with the second inner spacer in the second horizontal direction.

A semiconductor device comprising:

• a substrate;
• a first active pattern extending in a first horizontal direction on the substrate,
• a second active pattern extending in the first horizontal direction on the substrate, the second active pattern being spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction, a second width of the second active pattern in the second horizontal direction greater than a first width of the first active pattern in the second horizontal direction,
• a first plurality of nanosheets, each nanosheet of the first plurality of nanosheets being stacked and spaced apart from each other in a vertical direction on the first active pattern, each nanosheet of the first plurality of nanosheets having two sidewalls;
• a second plurality of nanosheets, each nanosheet of the second plurality of nanosheets being stacked and spaced apart from each other in the vertical direction on the second active pattern, a second width of each nanosheet of the second plurality of nanosheets in the second horizontal direction being greater than a first width of each nanosheet of the first plurality of nanosheets in the second horizontal direction, each nanosheet of the second plurality of nanosheets having two sidewalls;
• a gate electrode extending in the second horizontal direction on the first and second active patterns, the gate electrode surrounding each nanosheet of the first plurality of nanosheets and each nanosheet of the second plurality of nanosheets;
• a first source/drain region being in contact with both of the two sidewalls in the first horizontal direction of each nanosheet of the first plurality of nanosheets on the first active pattern;
• a second source/drain region being in contact with both of the two sidewalls in the first horizontal direction of each nanosheet of the second plurality of nanosheets on the second active pattern;
• a first inner spacer disposed between the gate electrode and the first source/drain region;
• a second inner spacer disposed between the gate electrode and the second source/drain region, a second thickness of the second inner spacer in the first horizontal direction being smaller than a first thickness of the first inner spacer in the first horizontal direction, a second width of the second inner spacer in the second horizontal direction being greater than a first width of the first inner spacer in the second horizontal direction;
• and
• a gate spacer disposed on both of the two sidewalls in the first horizontal direction of the gate electrode on a first upper surface of an uppermost nanosheet of the first plurality of nanosheets and on a second upper surface of an uppermost nanosheet of and the second plurality of nanosheets,
• wherein the first and second thicknesses of each of the first and second inner spacers in the first horizontal direction are each smaller than a thickness of the gate spacer in the first horizontal direction, and
• wherein a first portion of the first inner spacer overlaps with the second inner spacer in the second horizontal direction, and a second portion of the first inner spacer does not overlap with the second inner spacer in the second horizontal direction.