Monolithic stacked complementary transistor structures with dual work function metal gates

A device, comprising:

• a stacked transistor structure which comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type, and disposed over the first transistor;
• and
• a split gate structure which comprises a first dielectric isolation layer, a first metal gate structure of the first transistor, and a second metal gate structure of the second transistor which are isolated at least in part by the first dielectric isolation layer;
• wherein the second metal gate structure is embedded in the first dielectric isolation layer;
• and
• wherein the first metal gate structure is disposed below the first dielectric isolation layer.

A device, comprising:

• a substrate;
• a first stacked transistor structure and a second stacked transistor structure disposed on the substrate;
• wherein the first stacked transistor structure comprises:
• a first transistor of a first type, and a second transistor of a second type which is opposite the first type, and disposed over the first transistor;
• and
• a shared metal gate structure which comprises a first metal gate structure of the first transistor, and a second metal gate structure of the second transistor, wherein the second metal gate structure is embedded in the first metal gate structure;
• and
• wherein the second stacked transistor structure comprises:
• a third transistor of a first type, and a fourth transistor of a second type which is opposite the first type, and disposed over the third transistor;
• and
• a split gate structure which comprises a first dielectric isolation layer, a first metal gate structure of the third transistor, and a second metal gate structure of the fourth transistor which are isolated at least in part by the first dielectric isolation layer;
• wherein the second metal gate structure of the fourth transistor is embedded in the first dielectric isolation layer;
• and
• wherein the first metal gate structure of the third transistor is disposed below the first dielectric isolation layer.