Epitaxial growth of fully-strained and defect-free cfet superlattices using carbon doping and layered middle dielectric isolation

A workpiece, comprising:

• a multi-layered epitaxial stack disposed on a substrate, wherein the multi-layered epitaxial stack comprises a middle dielectric isolation (MDI) film disposed between a bottom field effect transistor (FET) module and a top FET module, wherein:
• the bottom FET module is disposed on the substrate;
• the bottom FET module comprises a plurality of first silicon germanium layers and silicon channel layers, wherein three of the first silicon germanium layers are alternately stacked with two of the silicon channel layers;
• the top FET module is disposed on the MDI film;
• the top FET module comprises a plurality of the first silicon germanium layers and the silicon channel layers, wherein two of the first silicon germanium layers are alternately stacked with two of the silicon channel layers;
• the MDI film comprises a plurality of the first silicon germanium layers and second silicon germanium layers, wherein three of the second silicon germanium layers are alternately stacked with two of the first silicon germanium layers, and wherein the second silicon germanium layers have a greater germanium concentration than the first silicon germanium layers;
• and
• the MDI film further comprises a bottom silicon epi layer disposed between the bottom FET module and the plurality of the first silicon germanium layers and the second silicon germanium layers and a top silicon epi layer disposed between the top FET module and the plurality of the first silicon germanium layers and the second silicon germanium layers.

A method of fabricating a film stack, comprising:

• depositing a bottom field effect transistor (FET) module on a substrate at a first temperature in a range from about 575° C. to about 625° C.;
• depositing a middle dielectric isolation (MDI) film on the bottom FET module at a second temperature in a range from about 575° C. to about 625° C.;
• and
• depositing a top FET module on the MDI film at a third temperature in a range from about 575° C. to about 625° C.;
• wherein
• the bottom FET module comprises a plurality of first silicon germanium layers and silicon channel layers, wherein the first silicon germanium layers and the silicon channel layers are alternately stacked on each other;
• the top FET module comprises a plurality of the first silicon germanium layers and the silicon channel layers, wherein the first silicon germanium layers and the silicon channel layers are alternately stacked on each other;
• and
• the MDI film comprises:
• a plurality of the first silicon germanium layers and second silicon germanium layers, wherein the first silicon germanium layers the second silicon germanium layers are alternately stacked on each other, and wherein the second silicon germanium layers have a greater germanium concentration than the first silicon germanium layers;
• a bottom silicon epi layer disposed between the bottom FET module and the plurality of the first silicon germanium layers and the second silicon germanium layers;
• and
• a top silicon epi layer disposed between the top FET module and the plurality of the first silicon germanium layers and the second silicon germanium layers.