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US 2026/0040665 A1Published application
Integrated circuit with i/o cpode devices
OwnerSung-Hsin YANG, Chen-Chieh CHIANG +3inventors
InventorsSung-Hsin YANG, Chen-Chieh CHIANG, Jia-Ren CHEN, Ying Ming WANG, Yuan Tsung TSAI
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Abstract
An integrated circuit includes both core transistors in a core circuitry region and I/O transistors in an I/O circuitry region. A layout of the integrated circuit includes semiconductor fins extending in a first direction and gate structures extending in a second direction. Core CPODE regions are formed between core transistors in a semiconductor fin. I/O CPODE regions are formed between I/O transistors in a semiconductor fin.
Claims20
A device, comprising:
- a first semiconductor fin extending in a first direction;
- a first of a first type transistor including a first source/drain region in the first semiconductor fin;
- a second of the first type transistor including a second source/drain region in the first semiconductor fin;
- a first trench isolation region between the first source/drain region and the second source/drain region;
- and
- a first dummy gate structure extending continuously in the first direction from a first portion of a top surface of the first semiconductor fin adjacent to the first source/drain region across the first trench isolation region to a second portion of the top surface of the first semiconductor fin adjacent to the second source/drain region.
3 more elements
A method, comprising:
- forming a first transistor including a first source/drain region in a first semiconductor fin and a first gate oxide on the first semiconductor fin, the first semiconductor fin extending in a first direction;
- forming a second transistor including the first gate oxide and a second source/drain region in the first semiconductor fin separated from the first source/drain region by a first trench isolation region;
- forming a first dummy gate structure overlying the first gate oxide and extending continuously across the first trench isolation region in the first direction;
- forming a third transistor including a third source/drain region in a second semiconductor fin and a second gate oxide on the second semiconductor fin, the first gate oxide being thicker than the second gate oxide, the second semiconductor fin extending in the first direction;
- forming a fourth transistor including the second gate oxide and a fourth source/drain region in the second semiconductor fin separated from the third source/drain region by a second trench isolation region;
- and
- forming a second dummy gate structure overlying the second gate oxide and extending continuously across the second trench isolation dummy gate structure in the first direction.
4 more elements
A device, comprising:
- I/O circuitry including:
- a first transistor of a first type;
- a second transistor of the first type;
- and
- an I/O CPODE structure between the first transistor of the first type and the second transistor of the first type;
- and
- core circuitry including:
- a first transistor of a second type;
- a second transistor of the second type;
- and
- a core CPODE structure between the first transistor of the second type and the second transistor of the second type.
8 more elements
Dependencies are inferred from the claim text.