P-Metal Gate First Gate Replacement Process for Multigate Devices

A method comprising:

• forming a first semiconductor layer over a p-type doped region of a substrate;
• forming a second semiconductor layer over an n-type doped region of the substrate;
• forming an isolation feature between the p-type doped region of the substrate and the n-type doped region of the substrate;
• and
• forming a gate stack around the first semiconductor layer and the second semiconductor layer, wherein the forming the gate stack includes:
• forming a gate dielectric layer having a first portion over the first semiconductor layer, a second portion over the second semiconductor layer, and a third portion over the p-type doped region of the substrate, the n-type doped region of the substrate, and the isolation feature between the p-type doped region of the substrate and the n-type doped region of the substrate,
• forming an n-type work function layer between the first portion of the gate dielectric layer and the third portion of the gate dielectric layer, wherein the first portion of the gate dielectric layer, the n-type work function layer, and the third portion of the gate dielectric layer fill a gap between the first semiconductor layer and the p-type doped region of the substrate, and
• forming a p-type work function layer between the second portion of the gate dielectric layer and the third portion of the gate dielectric layer, wherein the second portion of the gate dielectric layer, the p-type work function layer, and the third portion of the gate dielectric layer fill a gap between the second semiconductor layer and the n-type doped region of the substrate.

A transistor comprising:

• a semiconductor layer stack disposed over a semiconductor protrusion, the semiconductor layer stack including a first semiconductor layer disposed over the semiconductor protrusion and a second semiconductor layer disposed over the first semiconductor layer;
• a first source/drain structure and a second source/drain structure, wherein each of the first semiconductor layer and the second semiconductor layer extend along a first direction from the first source/drain structure to the second source/drain structure;
• an isolation structure abutting the semiconductor protrusion;
• and
• a gate stack disposed over the semiconductor layer stack, wherein the gate stack extends lengthwise along a second direction different than the first direction, wherein in a cross-sectional view along the second direction, the gate stack includes:
• a gate dielectric wrapping the first semiconductor layer and the second semiconductor layer, wherein the gate dielectric partially fills a gap between the first semiconductor layer and the second semiconductor layer,
• a p-type work function layer disposed over the gate dielectric and wrapping the first semiconductor layer and the second semiconductor layer, wherein the p-type work function layer fills a remainder of the gap between the first semiconductor layer and the second semiconductor layer,
• a bulk layer disposed over the p-type work function layer, and
• wherein the p-type work function layer has an end portion that extends along the second direction over the isolation structure, wherein the end portion includes a first portion having a first thickness and a second portion having a second thickness, wherein the first thickness is greater than the second thickness.