Semiconductor devices

A method of manufacturing a semiconductor device, the method comprising:

• forming a channel on a substrate, the channel including a transition metal dichalcogenide (TMD) containing a transition metal and a chalcogen element;
• forming first and second contact patterns on the channel;
• forming first and second source/drain electrodes on the first and second contact patterns, respectively, each of the first and second source/drain electrodes including a metal;
• forming a gate insulating layer on the substrate to cover the channel, the first and second contact patterns, and the first and second source/drain electrodes;
• and
• forming a gate electrode on a portion of the gate insulating layer,
• wherein each of the first and second contact patterns has a multi-layered structure including single layers stacked in a vertical direction substantially perpendicular to an upper surface of the substrate, each of the single layers including a transition metal dichalcogenide (TMD), and an intercalation material being disposed between the single layers.

A method of manufacturing a semiconductor device, the method comprising:

• forming an insulating layer on a substrate;
• forming a channel on the insulating layer, the channel including a first 2-dimensional material;
• forming first and second contact patterns on upper edge surfaces, respectively, of the channel, each of the first and second contact patterns including a second 2-dimensional material having an intercalation material disposed therein;
• forming first and second source/drain electrodes on the first and second contact patterns, respectively, each of the first and second source/drain electrodes including a metal;
• forming a gate insulating layer on an upper central surface and sidewalls of the channel, sidewalls of the first and second contact patterns, and sidewalls and upper surfaces of the first and second source/drain electrodes;
• forming a gate electrode on a portion of the gate insulating layer on the upper central surface of the channel, wherein a lower surface and a sidewall of the gate electrode are covered by the gate insulating layer;
• forming a first contact plug on an upper surface of the gate electrode;
• and
• forming second and third contact plugs extending through the gate insulating layer to contact upper surfaces of the first and second source/drain electrodes, respectively.