Gate patterning process for multi-gate devices

A semiconductor device, comprising:

• a substrate;
• a base fin extending from the substrate;
• a plurality of channel members disposed over the base fin;
• a gate dielectric layer wrapping around each of the plurality of channel members;
• an n-type work function metal layer around the gate dielectric layer;
• a p-type work function metal layer over the n-type work function metal layer;
• a passivation layer between the n-type work function metal layer and the p-type work function metal layer;
• a blocking layer over the p-type work metal layer;
• and
• a bulk metal layer over the blocking layer,
• wherein the passivation layer merges in space vertically between adjacent ones of the plurality of channel members to prevent the p-type work function metal layer from extending into the space.

A semiconductor device, comprising:

• a substrate;
• a plurality of nanostructures disposed one over another over the substrate;
• a gate dielectric layer wrapping around each of the plurality of nanostructures;
• an n-type work function metal layer around the gate dielectric layer;
• a p-type work function metal layer over the n-type work function metal layer;
• a passivation layer between the n-type work function metal layer and the p-type work function metal layer;
• a blocking layer over the p-type work function metal layer;
• and
• a bulk metal layer over the blocking layer,
• wherein the passivation layer and the block layer comprise silicon, silicon dioxide, or alumina.