Capacitor

A capacitor comprising:

• a silicon substrate having
• a first principal surface including a first region and a second region surrounding the first region,
• a second principal surface, and
• a porous part formed in the first region and having a plurality of micropores along a thickness direction defined with respect to the silicon substrate;
• a dielectric layer disposed over a surface of the porous part and the second region of the silicon substrate;
• a conductor layer disposed on the dielectric layer, and
• an interval between adjacent micropores of the plurality of micropores being ununiform in the thickness direction defined with respect to the silicon substrate,
• the conductor layer overlapping the first region and the second region in plan view in the thickness direction defined with respect to the silicon substrate,
• the silicon substrate having a doped layer containing a p-type dopant or an n-type dopant,
• the doped layer including
• a first doped layer disposed along the second region of the silicon substrate,
• a second doped layer disposed at a bottom part of the porous part of the silicon substrate, and
• a third doped layer disposed at a side part of the porous part of the silicon substrate,
• in the doped layer,
• the first doped layer being connected to the third doped layer, a smaller angle of two angles formed between the first doped layer and the third doped layer being an obtuse angle in a cross-sectional view in a second direction orthogonal to a first direction which is the thickness direction, and
• the second doped layer being connected to the third doped layer, a smaller angle of two angles formed between the second doped layer and the third doped layer being an obtuse angle in the cross-sectional view.