Semiconductor devices and data storage systems including the same

A semiconductor device, comprising:

• a first semiconductor structure including
• a substrate,
• circuit devices on the substrate, and
• first interconnection structure on the circuit devices, and
• a second semiconductor structure on the first semiconductor structure;
• the second semiconductor structure including
• a memory cell substrate including conductive patterns spaced apart from each other,
• gate electrodes including
• an upper select gate electrode,
• memory gate electrodes,
• a lower select gate electrode stacked and spaced apart from each other in a perpendicular direction, the perpendicular direction being perpendicular to a lower surface of the memory cell substrate below the memory cell substrate, and
• the upper select gate electrode, memory gate electrodes, and lower select gate electrode stacked in order from the lower surface of the memory cell substrate;
• a first isolation structure and a second isolation structure;
• each of the first and second isolation structures
• penetrating the gate electrodes,
• extending in a first direction intersecting the perpendicular direction, and
• spaced apart from each other in a second direction, the second direction intersecting the first direction;
• first channel structures
• penetrating the gate electrodes between the first isolation structure and the second isolation structure,
• extending in the perpendicular direction, and
• spaced apart from each other in the first direction;
• second channel structures
• penetrating the gate electrodes between the first isolation structure and the second isolation structure,
• extending in the perpendicular direction, and
• spaced apart from the first channel structures in the second direction;
• and a second interconnection structure below the gate electrodes and the first and second channel structures,
• wherein each of the first channel structures and the second channel structures includes
• first to fourth channel holes penetrating the gate electrodes in the perpendicular direction and spaced apart from each other,
• first to fourth data storage patterns in the first to fourth channel holes, and
• a first channel pattern extending from at least two or more of the first to fourth channel holes, and extending above at least two or more channel holes on the upper select gate electrode,
• the conductive patterns include a first conductive pattern extending in the first direction and a second conductive pattern spaced apart from the first conductive pattern in the second direction,
• the first conductive pattern is in contact with a portion of the first channel pattern of each of the first channel structures, and
• the second conductive pattern is in contact with a portion of the first channel pattern of each of the second channel structures.

A data storage system, comprising:

• a semiconductor storage device including
• a first semiconductor structure including
• circuit devices,
• a second semiconductor structure on one surface of the first semiconductor structure, and
• input/output pads electrically connected to the circuit devices;
• and
• a controller electrically connected to the semiconductor storage device through the input/output pad, and the controller configured to control the semiconductor storage device;
• the second semiconductor structure including
• a memory cell substrate including a conductive pattern and an insulating pattern surrounding a side surface of the conductive pattern,
• gate electrodes stacked and spaced apart from each other in a perpendicular direction, the perpendicular direction being perpendicular to a lower surface of the memory cell substrate below the memory cell substrate, and
• channel structures
• penetrating the gate electrodes,
• extending in the perpendicular direction, and
• the channel structures spaced apart from each other in a first direction,
• the first direction intersecting the perpendicular direction,
• wherein each of the channel structures includes
• a first channel hole penetrating the gate electrodes in the perpendicular direction,
• a second channel hole penetrating the gate electrodes in the perpendicular direction,
• the second channel hole spaced apart from the first channel hole,
• a first data storage pattern in the first channel hole;
• a second data storage pattern in the second channel hole;
• and
• a channel pattern including
• a first portion surrounded by the first data storage pattern and the second data storage pattern,
• a second portion extending from the first portion and extending above the first data storage pattern and the second data storage pattern, and
• a third portion extending from the second portion, and
• the third portion connecting the second portion of the channel pattern and an adjacent second portion of an adjacent channel pattern to each other, and
• the second portion of the channel pattern has a width decreasing from a lower surface to an upper surface.