Microelectronic devices, and related methods of forming microelectronic devices

A method of forming a microelectronic device, the method comprising:

• forming a stack structure comprising a vertically alternating sequence of insulative structures and other insulative structures arranged in tiers;
• forming dog-bone openings horizontally between an array region of the stack structure and a staircase structure of the microelectronic device, the dog-bone openings extending into the stack structure from an uppermost surface of the stack structure, each of the dog-bone openings comprising:
• a central elongated portion extending in a first horizontal direction;
• and
• two wide end portions at opposing horizontal ends of the central elongated portion;
• forming thin film transistors within the dog-bone openings and at each tier of the stack structure;
• and
• forming local word lines within the array region of the stack structure, each local word line comprising:
• a backbone member extending in a second horizontal direction orthogonal to the first horizontal direction;
• and
• extensions extending horizontally from the backbone member in a direction parallel or collinear to the first horizontal direction.

A microelectronic device, comprising:

• a stack structure comprising:
• tiers, wherein, within an array region of the stack structure, each tier respectively comprises:
• a first local word line comprising a first backbone member and first extensions extending orthogonally from the first backbone member in a first direction;
• and
• a second local word line comprising a second backbone member and second extensions extending orthogonally from the second backbone member in a second, opposite direction, wherein, at least multiple first extensions of the first local word line are each horizontally nested between second extensions of the second local word line, and wherein at least multiple second extensions of the second local word line are each horizontally nested between first extensions of the first local word line;
• and
• memory cells formed within the array region of the stack structure, each memory cell being coupled to and horizontally between at least one first extension of a first local word line and at least one a second extension of a second local word line;
• first in-tier word line decoder structures, each being coupled to a first backbone member of a respective first local word line on a horizontal side of the first backbone member opposite the first extensions, each of the first in-tier word line decoder structures comprising first thin film transistors;
• and
• second in-tier word line decoder structures, each being coupled to a second backbone member of a respective second local word line on a horizontal side of the second backbone member opposite the second extensions, each of the second in-tier word line decoder structures comprising second thin film transistors.