Semiconductor device having gate electrodes at different levels and data storage system including the same

A semiconductor device comprising:

• a first common gate electrode;
• a first individual gate electrode and a second individual gate electrode disposed at the same level, disposed at a level different from the first common gate electrode;
• a first vertical memory structure penetrating through the first common gate electrode and the first individual gate electrode, and spaced apart from the second individual gate electrode;
• a second vertical memory structure penetrating through the first common gate electrode and the second individual gate electrode, and spaced apart from the first individual gate electrode;
• a first common pass transistor electrically connected to the first common gate electrode;
• a first individual pass transistor electrically connected to the first individual gate electrode;
• and
• a second individual pass transistor electrically connected to the second individual gate electrode.

A data storage system, comprising:

• a semiconductor device including an input/output pad;
• and
• a controller electrically connected to the semiconductor device through the input/output pad, and configured to control the semiconductor device,
• wherein the semiconductor device includes:
• a first gate electrode;
• a second gate electrode disposed at a level different from the first gate electrode;
• a third gate electrode disposed at the same level as the second gate electrode and spaced apart from the second gate electrode;
• a first common pass transistor electrically connected to the first gate electrode;
• a first individual pass transistor electrically connected to the second gate electrode;
• and
• a second individual pass transistor electrically connected to the third gate electrode,
• wherein a size of a channel region of the first common pass transistor is greater than a size of a channel region of each of the first individual pass transistor and the second individual pass transistor.