Memory arrays, and methods of forming memory arrays
AssigneeLodestar Licensing Group LLC
InventorsChanghan Kim, Gianpietro Carnevale
Life of this patent
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Abstract
Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.
Claims20
A memory device, comprising:
- a stack structure including tiers vertically stacked relative to one another and respectively comprising conductive material and insulative material vertically neighboring the conductive material;
- and
- pillar structures respectively vertically extending through the stack structure, the conductive material of respective ones of the tiers of the stack structure having side surfaces horizontally proximate to the pillar structures and individually exhibiting an at least partially convex vertical cross-sectional shape.
A non-volatile memory device, comprising:
- a pillar structure defining a vertical string of non-volatile memory cells within a stack structure, the stack structure comprising:
- word line levels respectively comprising a conductive structure including sidewall horizontally neighboring the pillar structure and having an at least partially curved vertical profile;
- and
- insulative levels vertically alternating with the word line levels and respectively comprising an insulative structure including an additional sidewall horizontally neighboring the pillar structure and having a vertical profile different than the at least partially curved vertical profile of the conductive structure of the conductive structure of respective ones of the word line levels.
A 3D NAND Flash memory device, comprising:
- a stack structure including tiers vertically stacked relative to one another and respectively comprising:
- a word line level comprising:
- a conductive material having an upper surface, a lower surface, and an at least partially convex side surface extending from the upper surface to the lower surface;
- and
- a dielectric barrier material substantially covering the upper surface, the lower surface, and the at least partially convex side surface of the conductive material;
- and
- an insulative level vertically adjacent to the word line level and comprising an insulative material having a top surface, a bottom surface, and an at least partially concave side surface extending from the top surface to the bottom surface;
- and
- a pillar structure comprising semiconductor material vertically extending completely through the tiers of the stack structure, the pillar structure horizontally surrounded by:
- the at least partially convex side surface of the conductive material of the word line level of respective ones of the tiers;
- and
- the at least partially concave side surface of the insulative material of the insulative level of respective ones of the tiers.
Dependencies are inferred from the claim text.