Memory device having in-tier access line drivers
AssigneeMicron Technology, Inc.
InventorsEric S. Carman, Kamal M. Karda, Duane R. Mills
Life of this patent
Estimating the term…
Abstract
A variety of applications can include an apparatus having a three-dimensional (3D) memory device with sub-access line drivers to access lines embedded in a memory array of the 3D memory device. A sub-access line driver to an access line to a tier of memory cells of the memory array can include two transistors coupled to each other and the access line. A first transistor of the two transistors can be coupled at one end of the access line and the second transistor of the two transistors can be coupled at the other end of the access.
Claims20
A three-dimensional memory device comprising:
- an array of memory cells, each memory cell having an access transistor and a storage component, the array arranged in tiers of memory cells;
- an access line coupled to one or more access transistors of the array on a tier of the array;
- and
- a sub-access line driver coupled to the access line and embedded in the array in the tier in which the access line is located.
A method of forming a three-dimensional memory device, the method comprising:
- forming an array of memory cells arranged in tiers of memory cells with each memory cell having an access transistor and a storage component;
- forming an access line coupled to one or more access transistors of the array on a tier of the array;
- and
- forming a sub-access line driver embedded in the array in the tier in which the access line is located and coupled to the access line.
A method of operating a three-dimensional memory device comprising:
- operating on memory cells of an array of memory cells, each memory cell having an access transistor and a storage component, the array arranged in tiers of memory cells;
- and
- applying a voltage to an access line coupled to one or more access transistors of the array on a tier of the array by applying a set of voltages to a sub-access line driver coupled to the access line and embedded in the array in the tier in which the access line is located.
Dependencies are inferred from the claim text.