Semiconductor memory device

A semiconductor memory device comprising:

• a substrate;
• a first active pattern and a second active pattern, the first and the second active patterns being perpendicular to an upper surface of the substrate and the first active pattern being spaced apart from the second active pattern in a first direction;
• a mold pattern between the first and the second active patterns;
• a first word line between the mold pattern and the first active pattern;
• a second word line between the mold pattern and the second active pattern;
• a gate insulating layer between the first active pattern and the first word line and between the second active pattern and the second word line, wherein the gate insulating layer is on an upper surface of the mold pattern;
• storage node contact plugs that are respectively in contact with lower portions of the first and the second active patterns and which at least partially overlap the first and the second word lines;
• a bit line connecting upper portions of the first and the second active patterns;
• a separation insulating pattern between the storage node contact plugs and at least partially overlapping the mold pattern, wherein a portion of the separation insulating pattern is between the first and the second word lines and the storage node contact plugs;
• and
• conductive patterns between the separation insulating pattern and the storage node contact plugs, wherein the conductive patterns are in contact with the first and the second active patterns,
• wherein the storage node contact plugs comprise a first metal, and
• wherein the conductive patterns comprise a second metal different from the first metal.

A semiconductor memory device comprising:

• a substrate;
• an active pattern perpendicular to an upper surface of the substrate, the active pattern comprising a first side surface and a second side surface, the first side surface being opposite to the second side surface;
• a storage node contact plug in contact with a lower surface of the active pattern;
• a conductive pattern in contact with a lower portion of the first side surface of the active pattern and an upper surface of the storage node contact plug;
• a bit line in contact with an upper surface of the active pattern;
• a word line on the conductive pattern and adjacent to the first side surface of the active pattern;
• and
• a first insulating layer, a second insulating layer, and a third insulating layer sequentially arranged on the second side surface of the active pattern,
• wherein the third insulating layer comprises hydrogen, and
• wherein the second insulating layer prevents penetration of the hydrogen of the third insulating layer.