Two port sram device using forked nanosheet fets

A semiconductor storage device including a two-port SRAM cell, the two-port SRAM cell comprising:

• a first transistor connected to a first power supply supplying a first voltage at one of its nodes, to a first node at the other node, and to a second node at its gate;
• a second transistor connected to the first power supply at one of its nodes, to the second node at the other node, and to the first node at its gate;
• a third transistor connected to a first bit line at one of its nodes, to the first node at the other node, and to a first word line at its gate;
• a fourth transistor connected to a second bit line at one of its nodes, to the second node at the other node, and to the first word line at its gate, the first bit line and the second bit line constituting a first complementary bit line pair;
• a fifth transistor connected to a third bit line at one of its nodes, to the first node at the other node, and to a second word line at its gate;
• a sixth transistor connected to a fourth bit line at one of its nodes, to the second node at the other node, and to the second word line at its gate, the third bit line and the fourth bit line constituting a second complementary bit line pair;
• a seventh transistor connected to the first node at one of its nodes, to a second power supply supplying a second voltage different from the first voltage at the other node, and to the second node at its gate;
• and
• an eighth transistor connected to the second node at one of its nodes, to the second power supply at the other node, and to the first node at its gate,
• wherein
• the first to sixth transistors respectively include
• first to sixth nanosheets extending in a first direction, and
• first to sixth gate interconnects surrounding the first to sixth nanosheets, respectively, in a second direction vertical to the first direction and in a third direction perpendicular to the first and second directions,
• the seventh transistor includes
• seventh and eighth nanosheets extending in the first direction, and
• seventh and eighth gate interconnects surrounding the seventh and eighth nanosheets, respectively, in the second and third directions,
• the eighth transistor includes
• ninth and tenth nanosheets extending in the first direction, and
• ninth and tenth gate interconnects surrounding the ninth and tenth nanosheets, respectively, in the second and third directions,
• the fifth, third, second, ninth, and tenth nanosheets are formed in line in this order in the second direction,
• faces of the fifth and ninth nanosheets on a first side as one of the opposite sides in the second direction are exposed from the fifth and ninth gate interconnects, respectively, and
• faces of the second, third, and tenth nanosheets on a second side as the other side in the second direction are exposed from the second, third, and tenth gate interconnects, respectively.