Static random access memory

A static random access memory, comprising at least:

• a substrate;
• a plurality of fin structures located on the substrate;
• a plurality of gate structures located on the substrate and span the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor comprises a part of the gate structure spanning a part of the fin structure, and the plurality of transistors comprise:
• a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) together form a latch circuit;
• a first access transistor (PG1) and a second access transistor (PG2) connected to the latch circuit;
• and
• a first reading transistor (RPD) and a second reading transistor (RPG) connected in series, wherein the gate structure of the first reading transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1);
• wherein the first pull-down transistor (PD1), the second pull-down transistor (PD2), the first access transistor (PG1), the second access transistor (PG2), the first read transistor (RPD) and the second read transistor (RPG) each comprise a gate structure, wherein the gate structures of the first pull-down transistor (PD1), the second pull-down transistor (PD2), the first access transistor (PG1), the second access transistor (PG2), the first read transistor (RPD) and the second read transistor (RPG) all contain a P type work function metal layer, and an N type work function metal layer is located on the P type work function metal layer.