A method of manufacturing a power stage package, comprising:
- providing a printed circuit board comprising a first wiring layer, a second wiring layer, and an insulating layer disposed between the first and second wiring layers;
- forming two groups of transistors, each group of transistors comprising:
- a low-side transistor disposed on a first side of the printed circuit board, and
- a high-side transistor disposed on a second side of the printed circuit board opposite the first side, wherein a first electrode of the low-side transistor is electrically coupled to a second electrode of the high-side transistor through a first trace in the first wiring layer, a first via penetrating the insulating layer, and a second trace in the second wiring layer;
- forming a first package layer and a second package layer, wherein the first package layer is disposed on the first side of the printed circuit board and covering the low-side transistor, and the second package layer is disposed on the second side and covering the high-side transistor;
- and
- forming an exposed first redistribution layer configured to receive an input signal, wherein the first redistribution layer comprises:
- a first redistribution portion covering a portion of a first side surface of the first package layer;
- a second redistribution portion covering a portion of a second side surface of the first package layer;
- a third redistribution portion covering a portion of a third side surface of the second package layer, wherein the first redistribution portion is electrically coupled to the third redistribution portion through a third trace in the first wiring layer, a second via penetrating the insulating layer, and a fourth trace in the second wiring layer;
- a fourth redistribution portion covering a portion of a fourth side surface of the second package layer, wherein the second redistribution portion is electrically coupled to the fourth redistribution portion through a fifth trace in the first wiring layer, a third via penetrating the insulating layer, and a sixth trace in the second wiring layer;
- and
- a fifth redistribution portion covering a portion of a surface of the second package layer away from the printed circuit board, adjacent to the third and fourth redistribution portions, and connected to a first electrode of the high-side transistor in each transistor group through a fourth via penetrating the second package layer.