A decoder, comprising a processor, a memory storing an instruction executable for the processor, a communication interface and a bus configured to connect the processor, the memory and the communication interface, wherein the processor is configured to perform, when running the instruction, operations of:
- determining a mode parameter of a current block;
- and
- when the mode parameter indicates that a prediction value of the current block is determined according to a matrix-based intra prediction (MIP) mode, performing prediction on the current block according to the MIP mode based on an offset parameter, wherein the offset parameter for all block sizes and all MIP modes are the same.