Enabling efficient hash-based signature verification in processor-based devices

A method for enabling efficient hash-based signature verification, comprising:

• receiving, by a hash compute core circuit of a processor-based device from a process executing on a processor device of the processor-based device:
• a digit of a plurality of digits of a message digest;
• a signature value corresponding to the digit;
• and
• an initialized context value;
• generating, by the hash compute core circuit, a hash chain by, for Y times wherein Y is an integer value calculated using a value of the digit:
• updating the context value;
• and
• performing a hash operation on the signature value;
• transmitting, by the hash compute core circuit, an ending value of the hash chain to the process;
• and
• storing, by the process, the ending value of the hash chain.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed by a processor device, cause the processor device to:

• determine whether a message digest is valid;
• responsive to determining that the message digest is valid, transmit a digit of a plurality of digits of the message digest, a signature value corresponding to the digit, and an initialized context value to a hash compute core circuit;
• receive, from the hash compute core circuit, an ending value of a hash chain;
• and
• store the ending value of the hash chain;
• wherein the hash compute core circuit is configured to:
• receive, from the processor device, the digit of the plurality of digits of the message digest, the signature value corresponding to the digit, and the initialized context value;
• generate the hash chain by being configured to, for Y times wherein Y is an integer value calculated using a value of the digit:
• update the context value;
• and
• perform a hash operation on the signature value;
• and
• transmit the ending value of the hash chain to a process.