Background dac error calibration for sar adcs

A method of calibration of an analog-to-digital converter (ADC), the method comprising:

• performing ADC bit trials for an analog-to-digital (A/D) conversion of an input signal, wherein an ADC bit trial includes comparing the input signal to a state of a weighted circuit element;
• inputting a dither sequence into the ADC bit trials as dithered bit trials;
• determining an effect of the dither sequence on results of the dithered bit trials;
• and
• updating correction factors for the ADC bit trials using the determined effect of the dither sequence.

A non-transitory computer readable storage medium including instructions, that when performed using a controller for calibration circuitry of an analog-to-digital converter (ADC) cause the calibration circuitry to perform acts comprising:

• initiating dithered bit trials of the ADC, wherein a dithered bit trial inputs a dither sequence into ADC bit trials that include comparing an input signal to a state of a weighted circuit element of the ADC;
• determining a midpoint for the dithered bit trials;
• determining instantaneous errors in the dithered bit trials by comparing results of the dithered bit trials to the midpoint for values of the dither sequence;
• determining an error in the ADC bit trials using a determined convergence of the instantaneous errors in the dithered bit trials;
• and
• updating correction factors for the ADC bit trials according to the determined error in the ADC bit trials.