Voltage regulator noise mitigation with processor control
AssigneeQUALCOMM Incorporated
InventorsVijay Kiran KALYANAM, Todd Robert SUTTON, Suresh Kumar VENKUMAHANTI, Chi-Jui CHUNG
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Abstract
A method for voltage regulator noise mitigation with processor control is described. The method includes monitoring a power consumption of a sum of processor threads during thread pipeline execution. The method also includes detecting a voltage regulator noise when the power consumption exceeds a slew power threshold. The method further includes controlling slew ramp-up steps of all the processor threads according to a selected throttle control.
Claims20
A method for voltage regulator noise mitigation with processor control, the method comprising:
- monitoring a power consumption of a sum of processor threads during thread pipeline execution;
- detecting a voltage regulator noise when the power consumption exceeds a slew power threshold;
- and
- controlling slew ramp-up steps of all the processor threads according to a selected throttle control.
A voltage regulator noise mitigation system, comprising:
- a voltage regulator;
- a power management integrated circuit (PMIC);
- and
- a multi-threaded processor comprising a slew-ramp control circuit to control slew ramp-up steps of all processor threads according to a selected throttle control when a noise violation of the voltage regulator is detected due to power consumption of the multi-threaded processor exceeding a slew power threshold specified by the PMIC.
Dependencies are inferred from the claim text.