US 2026/0038618 A1 · WRITE LATENCY TESTING SYSTEMS AND METHODS

Abstract

The testing system comprises a processor and a local memory on a motherboard and an extension memory device under test (DUT). The local memory corresponds to a first address range within system memory and the extension memory DUT associated with a second address range within the system memory. The processor is operable to direct write latency testing of the extension memory DUT, including recording write latency measurement values. The recording can be done in a frequency table and the frequency table can be visualized (e.g., rendered, etc.) on a display. The testing comprises non-temporal write instructions that bypass processor caches. The extension memory DUT is compatible with a compute express link (CXL) protocol.

Claims20

Dependent claims

A method of determining write latency in a testing system comprising:

a motherboard comprising a processor and local memory;
and an external memory device under test (DUT) coupled to said motherboard, said method comprising:
a) storing an address within a memory range pertaining to said external memory DUT into registers of said processor;
b) storing a data piece of user data into registers of said processor;
c) starting a counter in said processor;
d) performing a write operation of said data piece from said registers to said address in said memory range of said external memory DUT;
e) recording a counter value of said counter upon completion of said write operation;
f) storing said counter value into a frequency table;
and
g) repeating steps a)-f) for a next address within said memory range pertaining to said external memory DUT and for a next data piece of said user data until said user data is written to said external memory DUT.

7 more elements

A testing system comprising:

a motherboard comprising:
a processor comprising registers;
and a local memory;
and
an extension memory device under test (DUT) coupled to said motherboard and comprising a memory address range associated therewith, wherein said processor is operable to execute test instructions to perform a method of determining write latency to said extension memory DUT, said method comprising:
a) storing an address within said memory range pertaining to said extension memory DUT into one or more registers of said processor;
b) storing a data piece of user data into one or more registers of said processor;
c) starting a counter in said processor;
d) performing a write operation of said data piece from said one or more registers to said address in said memory range of said extension memory DUT;
e) stopping said counter upon completion of said write operation;
f) storing a counter value from said counter into a frequency table;
and
g) repeating steps a)-f) for a next address within said memory range pertaining to said extension memory DUT and for a next data piece of said user data until said user data is written to said extension memory DUT, wherein said next data piece and said next address are selected based on a user supplied stride value.

10 more elements

Dependencies are inferred from the claim text.

Write latency testing systems and methods

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Write latency testing systems and methods

Life of this patent

Abstract

Claims20