Control circuit and semiconductor memory device

Abstract

The control circuit of this invention includes: a control unit, configured to generate a control signal indicating a delay amount; a delay line unit, configured to receive an input clock signal, and based on the control signal, perform a delay operation to generate an output clock signal; and a temporary delay amount selection unit configured to receive the output clock signal, generates a plurality of temporary delay signals that delay the output clock signal by a respective plurality of different temporary delay amounts, then performs a selection operation to select whichever of the temporary delay signals is closest in phase to the input clock signal, and outputs an output signal that indicates the temporary delay amount of the selected temporary delay signal. The control unit sets the delay amount according to the output signal indicating the temporary delay amount.

Dependencies are inferred from the claim text.