Non-volatile gain memory cell
AssigneeMicron Technology, Inc.
InventorsKamal Karda, Durai Vishak Nirmal Ramaswamy
Life of this patent
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Abstract
Methods, systems, and devices for a non-volatile gain memory cell are described. The memory cell may include a first transistor coupled with a digit line and comprising a gate terminal coupled with a word line, a ferroelectric material coupled with the first transistor and a plate line, a second transistor coupled with the plate line, and a third transistor coupled with the second transistor and the digit line. The second transistor including a gate terminal coupled with a node between the ferroelectric material and the first transistor. The third transistor including a gate terminal coupled with the word line.
Claims21
A memory cell, comprising:
- a first transistor coupled with a digit line and comprising a gate terminal coupled with a word line;
- a ferroelectric material coupled with the first transistor and a plate line, and configured to have a capacitance that is based at least in part on a voltage difference between the plate line and the digit line;
- a second transistor coupled with the plate line and comprising a gate terminal coupled with a node between the ferroelectric material and the first transistor, the second transistor configured to be activated based at least in part on the capacitance of the ferroelectric material;
- and
- a third transistor coupled with the second transistor and the digit line, and comprising a gate terminal coupled with the word line.
A method of writing a memory cell, comprising:
- deactivating a first p-type transistor, wherein the first p-type transistor comprises a gate terminal coupled with a node between a ferroelectric material and an n-type transistor and is activatable based at least in part on a capacitance of the ferroelectric material;
- deactivating a second p-type transistor, wherein the second p-type transistor comprises a gate terminal coupled with a word line and is activatable based at least in part on a voltage of the word line;
- activating the n-type transistor, wherein the n-type transistor is coupled with the ferroelectric material and a digit line;
- and
- applying a voltage difference across the ferroelectric material based at least in part on activating the n-type transistor and based at least in part on a logic state, wherein the capacitance of the ferroelectric material is based at least in part on the voltage difference and is representative of the logic state.
A method of reading a memory cell, comprising:
- deactivating an n-type transistor coupled with a ferroelectric material and a digit line;
- activating a first p-type transistor comprising a gate terminal coupled with a word line;
- applying a voltage to a plate line coupled with the ferroelectric material and with a second p-type transistor that comprises a gate terminal coupled with a node between the n-type transistor and the ferroelectric material, wherein a voltage that is based at least in part on a capacitance of the ferroelectric material develops on the node based at least in part on applying the voltage to the plate line;
- and
- sensing a signal on the digit line based at least in part on applying the voltage to the plate line, wherein a magnitude of the signal is based at least in part on the voltage on the node.
Dependencies are inferred from the claim text.