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US 2026/0038539 A1Published application
Shunting networks for access lines in a memory array
AssigneeMicron Technology, Inc.
InventorHernan Castro
Life of this patent
Estimating the term…
Abstract
Systems, methods, and apparatus for memory devices having shunting networks connected to access lines. In one approach, a memory device has memory cells arranged in a memory array. The memory cells are accessed using bitlines that are formed overlying the array. The bitlines are coupled to a shunting network that reduces the effective resistance of the bitlines. This improves performance when performing matrix vector multiplication using the memory array.
Claims21
An apparatus comprising:
- bitlines overlying and coupled to vertical strings of memory cells for summing output currents from the memory cells during multiplication;
- and
- a shunting network coupled to the bitlines.
An apparatus comprising:
- vertical interconnect;
- memory cells arranged in a plurality of sub-arrays, the memory cells accessed using access lines;
- and
- metal lines running in at least one plane above the access lines, wherein the metal lines are electrically coupled to the access lines by the vertical interconnect.
1 more element
An apparatus comprising:
- bitlines configured on a first wafer;
- and
- a shunting network configured on a second wafer that is bonded to the first wafer, the shunting network electrically coupled to the bitlines.
Dependencies are inferred from the claim text.