Semiconductor memory device and electronic system including the same

A semiconductor memory device, comprising:

• a substrate including a cell array region and an extension region;
• a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on a first side of the substrate in a first direction, the first direction being perpendicular to the first side of the substrate;
• the mold structure including the plurality of gate electrodes with a pad portion in a staircase structure on the extension region;
• a channel structure penetrating through the plurality of gate electrodes and extending on the cell array region in the first direction;
• a through via
• penetrating through a pad portion of a first gate electrode of the plurality of gate electrodes and a second gate electrode of the plurality of gate electrodes on the extension region,
• the second gate electrode being between the first gate electrode and the substrate, and
• the second gate electrode electrically connected to the pad portion of the first gate electrode;
• and
• an insulating pattern between the second gate electrode and the through via and surrounding a portion of a sidewall of the through via,
• wherein
• the insulating pattern includes
• an insulating structure including a first insulating layer and a second insulating layer surrounding three surfaces of the first insulating layer,
• a capping pattern between the insulating structure and the through via, and
• the capping pattern covers a first side of the insulating structure defined by a side surface of the first insulating layer and a side surface of the second insulating layer.

An electronic system, comprising:

• a main substrate;
• a semiconductor memory device on the main substrate;
• the semiconductor memory device including a peripheral circuit structure, and a cell structure stacked on the peripheral circuit structure;
• and
• a controller on the main substrate, the controller being electrically connected to the semiconductor memory device,
• wherein the cell structure includes
• a substrate including a cell array region and an extension region,
• a plurality of gate electrodes alternately stacked on the substrate in a first direction, and in a staircase structure on the extension region,
• a channel structure penetrating through the plurality of gate electrodes on the cell array region and extending in the first direction,
• a through via
• penetrating through a first gate electrode of the plurality of gate electrodes and a second gate electrode of the plurality of gate electrodes, and
• the second gate electrode being between the first gate electrode and the substrate,
• the through via connecting to the first gate electrode,
• an insulating pattern between the second gate electrode and a sidewall of the through via, and
• the through via is penetrating through the substrate and connected to the peripheral circuit structure, and
• the insulating pattern includes
• an insulating structure on a sidewall of the second gate electrode, and
• the insulating structure including
• a first insulating layer and a second insulating layer, and
• the second insulating layer surrounding the first insulating layer and in contact with upper and lower surfaces of the first insulating layer, and a capping pattern between the insulating structure and the through via.