Semiconductor memory device and electronic system including the same

A semiconductor memory device comprising:

• a substrate including a cell array region and an extension region;
• a mold structure on the substrate, wherein the mold structure includes a plurality of gate electrodes alternately stacked with a plurality of mold insulating layers in a first direction perpendicular to an upper surface of the substrate, and the plurality of gate electrodes include a pad portion disposed in a staircase structure on the extension region;
• a channel structure on the cell array region, wherein the channel structure extends through the plurality of gate electrodes in the first direction;
• a first through via on the extension region, wherein the first through via extends through a pad portion of a first gate electrode of the plurality of gate electrodes and through a second gate electrode of the plurality of gate electrodes, wherein the second gate electrode is between the first gate electrode and the substrate, and wherein the first through via is electrically connected to the pad portion of the first gate electrode;
• and
• an insulating pattern between the second gate electrode and the first through via, wherein the insulating pattern surrounds a portion of a sidewall of the first through via, wherein the insulating pattern includes
• an insulating structure including a first insulating layer and a second insulating layer surrounding three surfaces of the first insulating layer, and
• a capping pattern between the insulating structure and the sidewall of the first through via,
• wherein the capping pattern includes a first capping layer covering a first side of an insulating structure defined by a side surface of the first insulating layer and a side surface of the second insulating layer, and includes a second capping layer between the first capping layer and the sidewall of the first through via, and
• wherein a width of the second capping layer in the first direction decreases as a distance from the first through via increases.

An electronic system, comprising:

• a first substrate;
• a semiconductor memory device on the first substrate, wherein the semiconductor memory device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure;
• and
• a controller on the first substrate, wherein the controller is electrically connected to the semiconductor memory device, wherein the cell structure includes
• a second substrate including a cell array region and an extension region,
• a plurality of gate electrodes on the second substrate, wherein the plurality of gate electrodes are alternately stacked in a first direction perpendicular to an upper surface of the second substrate, and the plurality of gate electrodes provide a staircase structure on the extension region,
• a channel structure on the cell array region, wherein the channel structure is extends through the plurality of gate electrodes in the first direction,
• a first through via extending through a first gate electrode of the plurality of gate electrodes and through a second gate electrode of the plurality of gate electrodes, wherein the second gate electrode is between the first gate electrode and the second substrate, wherein the first through via is connected to the first gate electrode, and
• an insulating pattern between the second gate electrode and a sidewall of the first through via,
• wherein the first through via extends through the second substrate and is connected to the peripheral circuit structure, and the insulating pattern includes
• an insulating structure disposed on a sidewall of the second gate electrode and including a first insulating layer and a second insulating layer surrounding the first insulating layer,
• a liner insulating layer on an upper surface of the insulating structure, and
• a capping pattern between the insulating structure and the sidewall of the first through via,
• wherein the capping pattern includes a first capping layer on the insulating structure, and a second capping layer between the first capping layer and the sidewall of the first through via, and
• wherein a width of the second capping layer in the first direction decreases as a distance from the first through via increases.