Display device and electronic device including the same

A display device comprising:

• an element layer including a light emitting element;
• and
• a circuit layer including a pixel circuit unit connected to the light emitting element,
• wherein the circuit layer includes:
• a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
• a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node;
• a third transistor including a gate electrode connected to a second scan line, a first electrode connected to the third node, and a second electrode connected to the first node;
• a fourth transistor including a gate electrode connected to a third scan line, a first electrode connected to a first initializing voltage line, and a second electrode connected to the first node;
• a first capacitor electrode extending from the gate electrode of the first transistor;
• a second capacitor electrode which faces the first capacitor electrode to form a storage capacitor, and connected to a first driving voltage line;
• and
• an additional gate electrode connected to the gate electrode of the first transistor, and overlapping the first scan line to form a first boost capacitor, and
• the additional gate electrode is disposed on a layer different from a layer for the gate electrode of the first transistor, the second capacitor electrode, and the first scan line.

An electronic device comprising:

• a display panel including a pixel;
• a panel driver that drives the display panel;
• and
• a main processor that provides an image signal to the panel driver,
• wherein the pixel includes:
• a light emitting element;
• a first transistor connected between the light emitting element and a first driving voltage line, and the first transistor that operates based on a potential at a first node;
• a second transistor connected between a data line and a first electrode of the first transistor, and the second transistor that receives a first scan signal through a first scan line;
• a third transistor connected between the first node and a second electrode of the first transistor, and the third transistor that receives a second scan signal through a second scan line;
• a fourth transistor connected between the first node and a first initializing voltage line, and the fourth transistor that receives a third scan signal through a third scan line;
• a storage capacitor connected between the first node and the first driving voltage line;
• a first boost capacitor connected between the first node and the first scan line;
• and
• a second boost capacitor connected between the first node and the second scan line.