Machine Learning Using Four-Bit Binary Data Formats

A computing system comprising one or more processors and one or more non-transitory computer-readable media storing instructions that are executable by one or more processors to cause the computing system to perform operations, the operations comprising:

• obtaining a machine-learned model comprising one or more parameters having a four-bit binary format, wherein:
• the four-bit binary format correlates sixteen respective binary values to sixteen corresponding numerical values represented by the binary values;
• the sixteen numerical values are symmetric about a median;
• and
• a plurality of step sizes between the sixteen numerical values is non-uniform;
• obtaining one or more input values for one or more layers of the machine-learned model;
• and
• processing, based at least in part on the one or more parameters having the four-bit binary format, the one or more input values to generate one or more output values.

One or more non-transitory computer-readable media storing instructions that are executable by one or more processors to cause a computing system to perform operations, the operations comprising:

• obtaining a machine-learned model comprising one or more parameters having a four-bit binary format, wherein:
• the four-bit binary format correlates sixteen respective binary values to sixteen corresponding numerical values represented by the binary values;
• the sixteen numerical values are symmetric about a median;
• and
• a plurality of step sizes between the sixteen numerical values is non-uniform;
• obtaining one or more input values for one or more layers of the machine-learned model;
• and
• processing, based at least in part on the one or more parameters having the four-bit binary format, the one or more input values to generate one or more output values.

A processor device comprising:

• one or more registers storing one or more numerical values associated with a four-bit binary format, wherein:
• the four-bit binary format correlates sixteen respective binary values to sixteen corresponding numerical values represented by the binary values;
• the sixteen numerical values are symmetric about a median;
• and
• a plurality of step sizes between the sixteen numerical values is non-uniform;
• one or more programmable logic devices configured to retrieve, from the one or more registers based on a first binary value of the sixteen respective binary values, a corresponding first numerical value of the sixteen corresponding numerical values;
• and
• arithmetic hardware configured to perform operations based at least in part on the first numerical value.