Data storage device to efficiently manage map data and method of operating the same

A method of operating a data storage device including a memory device and a memory controller, the method comprising:

• generating, by the memory controller, a modified logic address based on a source logic address externally provided;
• extracting, by the memory controller, a key value based on the modified logic address;
• generating, by the memory controller, an index based on the modified logic address and the key value;
• and
• mapping, by the memory controller, the index to a physical address of the memory device.

A data storage device comprising:

• a memory device;
• and
• a memory controller configured to control the memory device,
• wherein the memory controller comprises:
• a mapping manager configured to generate an index based on a key value and a modified logic address, and generate mapping information by mapping the index and a physical address of the memory device, the key value being generated by extracting from the modified logic address generated by converting a source logic address externally provided at least once;
• and
• a processor configured to control the memory device to program write data into a position of the memory device, corresponding to the mapping information in response to a write request externally provided;
• wherein the key value extracted from specified bit digit values of the modified logic address, is generated with a random distribution, and
• wherein the write data is distributed and stored in the memory device based on the key value with the random distribution.

A data storage device comprising:

• a memory device;
• and
• a memory controller configured to generate a physical address corresponding to a source logic address based on a key value extracted from a modified logic address generated from the source logic address included in a write request in response to the write request externally provided,
• wherein, when the memory controller receives a stride patterned access request in which a difference between the source logic addresses included in continuously provided write requests is uniform, the key values extracted from the source logic addresses are identical, and the key values extracted from modified logic addresses generated based on the source logic addresses are different.