US 2026/0037265 A1 · PROCESSOR SUBROUTINE CACHE

Abstract

A processor includes an execution unit and a subroutine cache. The execution unit is configured to execute instructions. The subroutine cache us configured to provide instructions of a subroutine to the execution unit for execution. The subroutine cache includes subroutine instruction storage, a subroutine address register, and subroutine cache control logic. The subroutine control logic is configured to: identify a subroutine call instruction provided to the execution unit; determine whether an instruction of a subroutine invoked by the subroutine call instruction is stored in the subroutine instruction storage by evaluating a subroutine validity indicator that indicates whether at least a portion of the subroutine is stored in the subroutine instruction storage; and provide the instruction of the subroutine to the execution unit based on the subroutine validity indicator indicating that at least a portion of the subroutine is stored in the subroutine instruction storage.

Claims20

Dependent claims

A system, comprising:

an instruction storage configurable to store subroutines;
a first set of registers each configurable to store a value indicative of an address of a subroutine;
a second set of registers configurable to store validity indicators indicative of whether a register referenced by a subroutine is valid;
and
a control circuit configurable to:
receive a request indicative of a first subroutine that references a first register of the first set of registers;
determine, based on the validity indicators of the second set of registers, whether the first register is valid;
and
based on determining that the first register is valid, retrieve the first subroutine from the instruction storage based on the address stored in the first register.

6 more elements

Dependencies are inferred from the claim text.

Processor subroutine cache

Life of this patent

Processor subroutine cache

Life of this patent

Abstract

Claims20