Row-press mitigation circuit device and method for securing dram against data-disturbance errors

A system (computer system) comprising:

• a dynamic random-access memory device configured with a data-disturbance error mitigation circuit in a dynamic random-access memory array, the system comprising:
• a plurality of memory rows in a plurality of banks;
• and
• a controller, operatively coupled to the DRAM array, configured to write, read, and refresh elements of the DRAM array, the controller being further configured to:
• count, via a circuit, activation count of each memory row or a subset of memory rows in the plurality of memory rows in a unit time for a given bank;
• increment activation count upon detecting, via the circuit, a defective memory row being opened for a pre-determined time period;
• and
• refresh an adjacent memory row upon the activation count being above a specified Rowhammer threshold,
• wherein the activation count accounts for both Rowhammer and Row-press net effect to mitigate the defective memory row from repeated activation (Rowhammer) or leak charge on bit lines from being opened over time (Row-press).

A dynamic random-access memory device configured with a data-disturbance error mitigation circuit in a dynamic random-access memory array, the device comprising:

• a plurality of memory rows in a plurality of banks;
• and
• a controller, operatively coupled to the DRAM array, configured to write, read, and refresh elements of the DRAM array, the controller being further configured to:
• calculate, via a circuit, a probability value of a Rowhammer event in a memory row of a bank in the plurality of banks;
• count, via a timer register, row open time from a starting time when the memory row is open in the bank to a stopping time when the memory row is closed over a fixed-length time window in the bank;
• and
• recalculate the probability value of the Rowhammer event using an output of the timer register.