Apparatuses and methods for multiple power down and exit modes in memory devices

Abstract

A memory device can operate in multiple powerdown modes. A first powerdown mode powers down a memory rank by powering down one or more command address (CA) input buffers completely (e.g., turn off). A second powerdown mode powers down a memory rank by powering down one or more command address (CA) input buffers incompletely (e.g., a reduced operational state). In a non-limiting nonexclusive embodiment, the second powerdown mode powers down the one or more CA input buffers by placing the one or more CA input buffers in a low bias current state.

Dependencies are inferred from the claim text.