System level power management via externally controlled multi-compute unit power limiting

An apparatus for system level power management for a system-on-chip (SoC), comprising:

• at least one memory;
• and
• at least one processor coupled to the at least one memory, the at least one processor configured:
• to execute multiple compute units in the SoC;
• to receive a digital power meter (DPM) value for each compute unit, the DPM value comprising an estimated power consumption of the compute unit;
• and
• to modify, in response to an updated system power budget, a fair power resource allocation for each of the multiple compute units of the SoC based on a respective DPM value and the updated system power budget, the modifying occurring without relying on a maximum DPM value across compute units.

A non-transitory computer-readable medium having program code recorded thereon, the program code executed by a processor in a system-on-chip (SoC) and comprising:

• program code to execute multiple compute units in the SoC;
• program code to receive a digital power meter (DPM) value for each compute unit, the DPM value comprising an estimated power consumption of the compute unit;
• and
• program code to modify, in response to an updated system power budget, a fair power resource allocation for each of the multiple compute units of the SoC based on a respective DPM value and the updated system power budget, the modifying occurring without relying on a maximum DPM value across compute units.