Stacked die semiconductor package including an array of pillar structures

A semiconductor device assembly, comprising:

• a substrate;
• a first integrated circuit die over the substrate including a first plated hole that penetrates through the first integrated circuit die;
• a second integrated circuit die over the first integrated circuit die including a second plated hole that penetrates through the second integrated circuit die;
• and
• a pillar structure extending from the substrate that passes through the first plated hole and the second plated hole to electrically couple the first integrated circuit die, the second integrated circuit die, and the substrate.

An integrated assembly, comprising:

• a first semiconductor package, comprising:
• a first substrate;
• a first integrated circuit die over the first substrate including a first plated hole that penetrates through the first integrated circuit die;
• a second integrated circuit die over the first integrated circuit die including a second plated hole that penetrates through the second integrated circuit die;
• and
• a first pillar structure extending from the first substrate that passes through the first plated hole and the second plated hole to electrically couple the first integrated circuit die, the second integrated circuit die, and the first substrate;
• and
• a second semiconductor package over the first semiconductor package and electrically coupled with the first semiconductor package, comprising:
• a second substrate;
• a third integrated circuit die over the second substrate including a third plated hole that penetrates through the third integrated circuit die;
• a fourth integrated circuit die over the third integrated circuit die including a fourth plated hole that penetrates through the fourth integrated circuit die;
• and
• a second pillar structure extending from the second substrate that passes through the third plated hole and the fourth plated hole to electrically couple the third integrated circuit die, the fourth integrated circuit die, and the second substrate.

A method, comprising:

• forming a pillar structure on a substrate;
• forming, along a first edge of a first integrated circuit die, a first recess;
• forming, along a second edge of a second integrated circuit die, a second recess;
• placing the first integrated circuit die over the substrate,
• wherein placing the first integrated circuit die over the substrate uses the first recess to align the first integrated circuit die with the pillar structure;
• and
• stacking the second integrated circuit die over the first integrated circuit die,
• wherein stacking the second integrated circuit die over the first integrated circuit die uses the second recess to align the second integrated circuit die with the first integrated circuit die, and
• wherein stacking the second integrated circuit die over the first integrated circuit die uses a bearing surface of the pillar structure to form a gap between the second integrated circuit die and the first integrated circuit die.

A method, comprising:

• forming a pillar structure on a substrate;
• forming a first plated through-hole that penetrates through a first integrated circuit die;
• forming a second plated through-hole that penetrates through a second integrated circuit die;
• placing the first integrated circuit die over the substrate,
• wherein placing the first integrated circuit die over the substrate includes passing the pillar structure through the first plated through-hole and electrically coupling the first integrated circuit die with the substrate using the pillar structure;
• and
• stacking the second integrated circuit die over the first integrated circuit die,
• wherein stacking the second integrated circuit die over the first integrated circuit die includes passing the pillar structure through the second plated through-hole and electrically coupling the second integrated circuit die with the first integrated circuit die and the substrate using the pillar structure.