User-enabled test mode patterns
AssigneeMicron Technology, Inc.
InventorsGianluca Coppola, Angelo Sergio, Marco Lorenzo Valerio Tagliaferri, José Maria De Matos Cortes Antunes Calcada, Gennaro Schettino
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AssigneeMicron Technology, Inc.
InventorsGianluca Coppola, Angelo Sergio, Marco Lorenzo Valerio Tagliaferri, José Maria De Matos Cortes Antunes Calcada, Gennaro Schettino
Estimating the term…
Methods, systems, and devices for user-enabled test mode patterns are described. A host system may transmit a command to enable transmission of test signals by a memory system according to a test pattern. The host system may determine the test pattern and parameters for transmission of the test signals based on a capability of the memory system. The memory system may receive the command to transmit the test signals according to multiple parameters, including the test pattern, associated with transmission of the test signals. The parameters may include a speed, gear, rate, clock, mode, lane, hold-off time, scrambling mode, time duration, password, or any combination thereof. The memory system may verify a capability to transmit the test signals in accordance with the parameters and transmit a confirmation message to the host system. The memory system may transmit, in accordance with the parameters and transmitting the confirmation message, the test signals.
An apparatus for operating a memory system, comprising:
An apparatus for operating a host system, comprising:
A method for operating a memory system, comprising:
Dependencies are inferred from the claim text.