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US 2026/0031141 A1Published application
Systems and methods to mitigate cycle time degradation by nbti effect on pdp sram
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Hsin Nien, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen
Life of this patent
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Abstract
A memory circuit includes a memory array comprising a plurality of memory cells. The memory circuit includes a first pre-charge circuit coupled to at least one access line electrically connected to the plurality of memory cells and configured to be in a first state during a standby mode of the memory array. The memory circuit includes a second pre-charge circuit coupled to the at least one access line and configured to be in a second state during the standby mode.
Claims20
A memory circuit, comprising:
- a memory array comprising a plurality of memory cells;
- a first pre-charge circuit coupled to at least one access line electrically connected to the plurality of memory cells, and configured to be in a first state during a standby mode of the memory array;
- and
- a second pre-charge circuit coupled to the at least one access line, and configured to be in a second state during the standby mode.
1 more element
A memory circuit, comprising:
- a memory array comprising a plurality of memory cells;
- a pre-charge circuit coupled to a first access line and a second access line electrically connected to the plurality of memory cells, and configured to be in a low state during a standby mode of the memory array;
- and
- an equalizer circuit coupled to the first access line and the second access line, and configured to be in a high state during the standby mode.
1 more element
A method, comprising:
- activating a first pre-charge circuit, coupled to at least one access line electrically connected to a plurality of memory cells of a memory array, during a standby mode of the memory array, wherein activating the first pre-charge circuit charges the at least one access line to a supply voltage;
- and
- deactivating a second pre-charge circuit, coupled to the at least one access line, during the standby mode of the memory array, wherein deactivating the second pre-charge circuit suspends charging the at least one access line.
Dependencies are inferred from the claim text.